(1) Field of the Invention
The present invention relates to EL display panels, EL display apparatuses, and methods of manufacturing EL display panels, and particularly relates to an EL display panel and an EL display apparatus used for an active-matrix display apparatus, and a method of manufacturing an EL display panel used for an active-matrix display apparatus.
(2) Description of the Related Art
Thin film transistors (TFT) are used as a switching device for selecting pixel or a driving device for display device in active-matrix drive display apparatuses such as liquid crystal display apparatuses and organic EL display apparatuses.
TFTs are used for active-matrix substrate of display apparatuses, and active research and development has been done for improving the capability. In particular, along with the increase in the size and increased definition of display apparatus, there is a demand for high driving capability TFT. In this context, semiconductor thin films (polysilicon and microcrystalline silicon) crystallized for channel layers (active layers) have been attracting attention.
As a crystallizing process of a semiconductor thin film, instead of the conventional high temperature process technology in which a treatment temperature of 1000 degrees Celsius or higher is used, a low temperature process utilizing a treatment temperature of 600 degrees Celsius or lower has developed. In the low temperature process, it is not necessary to use expensive substrate such as highly heat resistant quartz, which reduces manufacturing cost.
Laser annealing which uses laser beam for heating has attracted attention as a type of low temperature process. Laser annealing includes locally heating and melting, by irradiating laser beam, non-single crystal semiconductor thin film such as amorphous silicon laminated on an insulating substrate with low heat resistance such as glass, and crystallizing the semiconductor thin film during the cooling process. Mobility of carriers in the crystallized semiconductor thin film increases, improving capability of the thin film transistor (for example, see Patent Literature 1: Japanese Unexamined Patent Application Publication No. H07-235490).
Majority of thin film transistors have a bottom-gate structure in which gate electrodes are arranged in a level lower than the channel layer. The following describes a conventional bottom-gate thin film transistor with reference to FIGS. 23, 24A to 24C, and 25. FIG. 23 is a planar view of the conventional thin film semiconductor device corresponding to one pixel of the display apparatus. FIG. 24A is a cross-sectional view of the conventional thin film semiconductor device for a display apparatus along the line X1-X1′ in FIG. 23. FIG. 24B is a cross-sectional view of the conventional thin film semiconductor device for display apparatus along the line X2-X2′ in FIG. 23. FIG. 24C is a cross-sectional view of the conventional thin film semiconductor device for display apparatus along the line Y-Y′ in FIG. 23. FIG. 25 is a perspective view corresponding to FIG. 24A, illustrating major components of the conventional thin film semiconductor device for display apparatus from the cross section X1-X1′ in FIG. 23.
As illustrated in FIGS. 23, 24A to 24C, and 25, the conventional thin film semiconductor device 9 for display apparatus includes a gate line 921 formed along the row direction of the pixel, a source line 922 formed along the column direction of the pixel, and a thin film transistor 910 arranged at a position in which the gate line 921 and the source line 922 cross each other.
As illustrated in FIG. 24A, the thin film transistor 910 is a bottom-gate thin film transistor, and is a multilayer structure including a gate electrode 910G, a gate insulating film 930, a semiconductor layer (channel layer) 911, and one pair of source electrode 910S and a drain electrode 910D sequentially formed on a substrate 900.
As illustrated in FIGS. 23 and 24A, the gate electrode 910G extends from the gate line 921, and formed in a first metal layer ML1′ in which the gate line 921 is also formed. The gate insulating film 930 is formed on the substrate 900 to cover the gate line 921 and the gate electrode 910G. The semiconductor layer 911 is formed on the gate insulating film 930 in an island shape overlapping the gate electrode 910G. One pair of the source electrode 910S and the drain electrode 910D is formed overlapping part of the semiconductor layer 911 and arranged separately opposite to each other. The source electrode 910S and the drain electrode 910D are formed in a second metal layer ML2′, in which the source line 922 is also formed. Note that, an interlayer insulating film 940 is laminated covering the thin film transistor 910, the gate line 921, and the source line 922.
Here, when forming the semiconductor layer 911 in the bottom-gate thin film transistor 910 by forming amorphous silicon on the gate electrode 910G and crystallizing the amorphous silicon by laser annealing, the heat of laser annealing radiates through the gate electrode 910G when melting the amorphous silicon. Accordingly, it is preferable that the gate electrode 910G is made of a material with small heat conductivity for suppressing the radiation of the heat at the time of laser annealing for crystallizing the semiconductor layer 911.
In the gate line 921, high line resistivity causes delay in signals or uneven display due to voltage drop. Particularly, increased driving frequency due to increased panel dimension makes the panel more likely to be affected by the line resistivity. Therefore, it is preferable that the gate line 921 is composed of the material with low resistivity (specific resistance).
As described above, the gate electrode 910G and the gate line 921 are formed in the same layer. Thus, they are usually made of the same material. Thus, when the gate electrode 910G is made of the material with small heat conductivity in consideration of crystallizing the semiconductor layer 911, the gate line 921 is also made of the material with small heat conductivity. Alternatively, when the gate line 921 is made of the material with small resistivity in consideration of the line resistance of the gate line 921, the gate electrode 910G is also made of the material with small resistivity.
However, most of metal with small heat conductivity has high resistivity. Thus, it is difficult to satisfy both the concern in crystallizing the semiconductor layer 911 and the concern in line resistance of the gate line 921 at the same time.
In order to address this problem, the thin film semiconductor device for display apparatus which solves these concerns has been proposed (see Patent Literature 2: Japanese Unexamined Patent Application Publication No. 2007-047808). Patent Literature 2 discloses a structure in which the gate line is divided into two portions for satisfying both the heat conductivity of the gate electrode and reduced resistance in the gate line.
More specifically, in the thin film semiconductor device for display apparatus according to Patent Literature 2, the gate line includes an integral portion integrally formed with the gate electrode and a separate portion connected to the integral portion through a contact hole. In addition, the integrated portion of the gate line three-dimensionally crosses the source line interposing the gate insulating film in between. The integrated portion of the gate electrode and the gate line are made of material with lower heat conductivity than the separate portion of the gate line, while the separate portion of the gate line is made of material with lower resistivity than the gate electrode.